MIPS Pipelined Processor

I designed and implemented a 32-bit MIPS pipelined processor and synthesized a 32-bit ALU and counter module on the Basys 3 FPGA. This project required a deep understanding of computer architecture and digital logic to optimize instruction execution. I conducted extensive analysis of timing, power consumption, and resource utilization in Vivado to refine performance while minimizing hardware overhead. To validate the system, I implemented various test cases and monitored the output through FPGA LEDs, ensuring correct functionality. This project strengthened my expertise in FPGA design, Verilog coding, and hardware testing methodologies.